BITS Pilani (Goa Campus) Research Fellow Opportunity (PhD Aspirants) — CREST Sponsored Project

This content is prepared strictly from the official job notification you provided. Any details not stated in the notification are explicitly marked as “Not mentioned in the official notification”.

Organization Details

Organization Name (English)	Birla Institute of Technology & Science, Pilani (BITS Pilani) – K. K. Birla Goa Campus
Organization Name (Hindi)	बिरला प्रौद्योगिकी एवं विज्ञान संस्थान, पिलानी (BITS पिलानी) – के. के. बिरला गोवा परिसर
Department / Unit	Electrical and Electronics Engineering
Project Sponsorship / Context	CREST sponsored research project (position is under CREST funded project)

Post / Designation Details

The notification states that this opportunity is applicable only to PhD aspirants.

Field	Details
Designation (English)	Research Fellow
Designation (Hindi)	रिसर्च फेलो (शोध फेलो)
Number of Vacancies	Not mentioned in the official notification
Employment Type	Research Fellow (CREST project; PhD aspirant focused). Exact employment type wording (e.g., permanent/contract/full-time) is not mentioned in the official notification.
Job Location (as stated)	BITS Pilani, K. K. Birla Goa Campus, Goa

Structured Location Fields (as requested)

streetAddress	city	state	country	postalCode
Not mentioned in the official notification	Not mentioned in the official notification	Goa (mentioned in the official notification)	Not mentioned in the official notification	Not mentioned in the official notification

Base Salary / Fellowship

baseSalary	₹37,000 – ₹42,000 per month (based on year of PhD and performance)
Additional Pay/Benefits	Not mentioned in the official notification

Project Details

Project Title	Low-Noise Adaptation of State-of-the-Art High-Speed Comparators Using Random Noise Cancellation Techniques and ML-Assisted Optimization
Project Code	TOPS/12/25/105
Broad Area	Analog Circuit Design, High-speed Comparators, VLSI
Duration	As per BITS Pilani norms (the notification directs candidates to BITS Pilani PhD norms/eligibility process)

Scope of Work (as described in the notification)

Design, optimization, and silicon validation of low-noise high-speed dynamic comparators.
ML-assisted design-space optimization.
Post-silicon characterization in 65 nm.
Interaction with industry collaborators.

Eligibility Criteria

Eligibility Component	Requirement (as stated)
Who Can Apply	Only PhD aspirants
Essential Qualification	Post Graduate or Graduate degree in EEE / Electronics / Communication / Instrumentation (or equivalent discipline) from a recognized university
GATE Requirement	GATE score is not mandatory
Desirable Qualification / Skills	Strong background in VLSI and analog circuit design; knowledge of Cadence Virtuoso is an added advantage
PhD Program Eligibility Reference	The notification asks candidates to check BITS Pilani PhD eligibility/qualification process at the referenced link (provided below in the “Official Links” section).

Additional eligibility items such as experience requirements, nationality/domicile rules, medical/physical standards, and category-based relaxations are not mentioned in the official notification.

Important Dates

Event	Date
Last Date to Apply	28 February 2026
Application Start Date	Not mentioned in the official notification
Interview / Test / Shortlisting Schedule	Not mentioned in the official notification
Admit Card / Exam Date / Result Date	Not mentioned in the official notification

Application Process

Applicants must submit CV + Cover Letter. The cover letter should clearly demonstrate alignment/justification with the roles, responsibilities, and requirements mentioned in the notification.

Mode of Application

Online (via Google Form link provided in the notification)

Step-by-Step (as stated)

Prepare your updated CV.
Prepare a cover letter showing your alignment/justification with the roles, responsibilities, and requirements.
Submit the application through the Google Form link provided in the notification.

Application Link

Google Form	https://forms.gle/T93y3xGSrR8AHGAg6
Offline Submission / Postal Address	Not mentioned in the official notification
Email Submission	Not mentioned in the official notification

Selection Process

The notification does not describe the selection process (no written stages such as screening test/interview/document verification/medical examination are mentioned).

Age Limit

Age limit details (minimum age, maximum age, cutoff date, and relaxation rules) are not mentioned in the official notification.

Reservation Details

Reservation details (category-wise vacancies, PwBD/ExSM provisions, relaxations, or horizontal reservation rules) are not mentioned in the official notification.

Application Fees

Application fee details (category-wise fees, payment mode, or exemptions) are not mentioned in the official notification.

Accommodation

Hostel accommodation is provided subject to availability and institute rules at the time of joining.

Investigators / Supervisors Mentioned

Role	Name (as stated in the notification)
Principal Investigator	Dr. Ria Rashid
Co-Principal Investigator	Mr. Komala Krishna K.

Helpline Numbers / Contact Information

Helpline numbers, support email, or contact office details are not mentioned in the official notification.

Official Links (as referenced in the notification)

BITS Pilani PhD Program Information / Eligibility Reference (as cited in the notification): http://www.bitsadmission.com/phmain.aspx

Birla Institute of Technology & Science, Pilani (BITS Pilani) Recruitment 2026